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    • ISSN: 1793-821X
    • Frequency: Quarterly (2013-2014); Bimonthly (Since 2015)
    • DOI: 10.18178/JOCET
    • Editor-in-Chief: Prof. Haider F. Abdul Amir
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School of Science and Technology Universiti Malaysia Sabah, Malaysia.
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JOCET 2014 Vol.2(1): 101-103 ISSN: 1793-821X
DOI: 10.7763/JOCET.2014.V2.100

An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

Jiang Wang and Leif Arne Ronningen
Abstract—Design and functional implementation of a 16-point pipelined FFT architecture is presented. The architecture is based on the radix-4 algorithm. By exploiting the regularity of the algorithm, butterfly operation and multiplier modules were designed. The architecture adopts four butterflies, and the pipeline stage is optimized to balance the processing speed and the area. It was modeled by VHDL, and synthesized in FPGA. By adopting this architecture, the data throughput could be 2M/s. It is extensible for high point FFT.

Index Terms—Fast Fourier transform (FFT), modular architecture, pipeline, VLSI design.

The authors are with the Department of Telematics, NTNU, Trondheim 7491, Norway (e-mail: jiangw@item.ntnu.no).

[PDF]

Cite:Jiang Wang and Leif Arne Ronningen, "An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs," Journal of Clean Energy Technologies vol. 2, no. 1, pp. 101-103, 2014.

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